High-speed data communication systems frequently rely on dock and data recovery (CDR) circuits within the receiver rather than transmitting a reference dock with the data. For example, serial data communication may include the use of a serializer-deserializer (SERDES) at each end of a communication link. Within a SERDES, a CDR may extract a dock that is embedded in the incoming data stream, Once a dock is recovered, the clock is used to sample the incoming data stream to recover individual bits.
A bang-bang CDR scheme is widely used in digital logic to identify the best dock phase to capture the received data. In a bang-bang CDR scheme, the received signal is oversampled to obtain data samples and crossing samples (also referred to as edge samples). A bang-bang CDR uses the data samples and the crossing samples to determine if the data sampling phase should be adjusted, in which direction the data sampling phase should be adjusted, and where to stop the adjustment. Once the data sampling phase dithers around the “best” sampling position, the bang-bang CDR is locked.